CISC to RISC (and back again?)
Everybody knows that x86 chips are CISC chips. An everlasting battle between CISC and RISC fans has started to fade but the question remains, is there anything in common between a modern x86 processor, let's say the Pentium 4 , and the CISC remains of the past? Most readers will agree that modern x86 chips are essentially RISC cores with a CISC frontend and "emulated" extended instructions.
Looking at the x86 instruction set can be fun. Whole sets of instructions appear totally out of context today, for example, the ASCII adjust family (AAA, AAD, AAM, AAS), the decimal adjust family (DAA, DAS), the XLAT instruction and several others that have propably never been generated by a compiler. Consider the XLAT instruction, that translates a byte to another byte by using a lookup table. Using it would have been a shortcut to loading the register, calculating a memory address with it (remember that the 16-bit processors had very limited address calculation facilities, in stark contrast to the 386 and later processors) and loading the resulting value. Today the XLAT instruction is propably emulated and executes much slower than an explicit load-lookup-store sequence of generic RISC-like instructions. As a matter of fact, since the Pentium II many of these instructions are prohibitively slow and nobody noticed. In that sense, the x86 became RISC-like.
On the other hand, the x86 instruction set has grown significantly with a huge number of extensions: MMX, MMXext, 3dnow, 3dnow-ext, SSE, SSE2 and SSE3. Many more, relatively minor additions have also been made (anyone remember cmpxchg8b8?). The point is that all these extensions, especially the SIMD ones, are like the 16-bit remnants of the past in the fact that they address a very specific problem which we find significant today but which may also become trivial in the future or be solved in another way. In that sense, the x86 continues the CISC tradition by providing instructions for very specific tasks. However, things do change. If for example multi-core chips become popular it might be easier to have 16 simple cores than 2 complex ones. A simple core might be hard pressed to compute complex multi-unit instructions like MMX and SSE and prefer simpler RISC-like instructions. In that case a multi-threaded, instead of SIMD, approach may be much faster and the whole class of SIMD may be deprecated.
In the course of many years the x86 architecture has evolved significantly. The CISC heritage will never change but the modern Athlon64 in 64-bit mode is a much better processor not only in terms of performance but also by the quality of its design. The future is going to be a very interesting place.
PKT
Looking at the x86 instruction set can be fun. Whole sets of instructions appear totally out of context today, for example, the ASCII adjust family (AAA, AAD, AAM, AAS), the decimal adjust family (DAA, DAS), the XLAT instruction and several others that have propably never been generated by a compiler. Consider the XLAT instruction, that translates a byte to another byte by using a lookup table. Using it would have been a shortcut to loading the register, calculating a memory address with it (remember that the 16-bit processors had very limited address calculation facilities, in stark contrast to the 386 and later processors) and loading the resulting value. Today the XLAT instruction is propably emulated and executes much slower than an explicit load-lookup-store sequence of generic RISC-like instructions. As a matter of fact, since the Pentium II many of these instructions are prohibitively slow and nobody noticed. In that sense, the x86 became RISC-like.
On the other hand, the x86 instruction set has grown significantly with a huge number of extensions: MMX, MMXext, 3dnow, 3dnow-ext, SSE, SSE2 and SSE3. Many more, relatively minor additions have also been made (anyone remember cmpxchg8b8?). The point is that all these extensions, especially the SIMD ones, are like the 16-bit remnants of the past in the fact that they address a very specific problem which we find significant today but which may also become trivial in the future or be solved in another way. In that sense, the x86 continues the CISC tradition by providing instructions for very specific tasks. However, things do change. If for example multi-core chips become popular it might be easier to have 16 simple cores than 2 complex ones. A simple core might be hard pressed to compute complex multi-unit instructions like MMX and SSE and prefer simpler RISC-like instructions. In that case a multi-threaded, instead of SIMD, approach may be much faster and the whole class of SIMD may be deprecated.
In the course of many years the x86 architecture has evolved significantly. The CISC heritage will never change but the modern Athlon64 in 64-bit mode is a much better processor not only in terms of performance but also by the quality of its design. The future is going to be a very interesting place.
PKT
posted by PKT at 1:09 μ.μ.
1 Comments:
It is mostly argued here that, even though x86 processors have been RISC for ages (essentially, ever since the P6 and K6 cores), the extensions that have been adopted along the way somehow continue the legacy of CISC. I don't really agree. The later instructions, excluding the SIMD ones for a moment, are usually not particularly complex, and not exactly equivalent to a series of simpler instructions.
For example, a lot of instructions, like the mentioned CMPXCHG8B8, were added to serve multi-tasking environments. Let me explain: When the operating system supports multiple processes running at the same time, a lot of synchronisation primitives are used to ensure the smooth operation of the system. While this can always be implemented using busy-loops ("spinning"), this is horribly inefficient, so better methods are sought after. Well, turns out that these methods are possible, if certain complex operations are guaranteed to be atomic. That is, noone cares if the complex instruction is more efficient or not compared to the series of simple instructions, as long as the full complex operation is either performed as a whole or not at all.
Another family of instructions, namely the CMOV family ("conditional move" for the uninitiated), deserve special mention as well (note that these also serve for atomicity): They can help eliminate branches from the code. These instructions assign a value if a certain condition is met; this means that, while of course the instructions after them depend on the condition for the actual value that was assigned, the flow of the instructions remains unaltered, regardless of the condition. With today's long pipelines, this is greatly appreciated.
Finally, the SIMD instructions. OK, these serve somewhat niche purposes, but they serve those really well. Not that they're not due to marketing to some extent; the latest SSE3 instructions leave one wondering what's the point. But in general, even though these are large extensions to the instruction set, I would argue that (a) MMX is slowly becoming obsolete anyway, and (b) 3DNow! / SSE are slowing causing x87 to become obsolete.
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